The semiconductor industry is undergoing a significant architectural shift, with gate-all-around (GAA) nanosheet transistors replacing FinFETs in advanced logic nodes of 3nm and beyond. This transition is driven by the need for increased performance and scalability, particularly in the context of the AI revolution. Imec, along with its industrial partners, is at the forefront of this change, working to make CFET-based devices manufacturable and scalable. The focus is on developing integration modules and standard cell configurations that can support the transition to CFET-based transistor architectures, enabling 4.5-track (4.5T) and below standard cells.
In this article, we delve into two key aspects of CFET integration and scalability. Firstly, we explore the benefits of backside contacting for CFET devices, which offers improved performance and survival rate for bottom pFETs. By directly contacting the source/drain junctions from the wafer backside, the contact resistance is reduced, and the process window for top device source/drain formation is enlarged. This approach also reduces routing congestion in the BEOL at the wafer frontside, contributing to overall device performance.
Secondly, we examine the development of a novel dipole-based gate stack for threshold voltage tuning. This approach is particularly relevant for nanosheet-based devices, where space between stacked nanosheets is limited. By incorporating dipole-forming metal, such as lanthanum (La) atoms, between the SiO2 interlayer and the HfO2 high-k dielectric layer, the threshold voltage (Vt) of the device can be tuned. This enables devices to operate at different Vt values, balancing the demands of high performance computing and ultra-low power operation.
The article also discusses the integration of these modules and approaches, highlighting the importance of design-technology co-optimization (DTCO) studies. These studies aim to identify scalable standard cell configurations and performance boosters that offer the best tradeoff in terms of power, performance, area, and cost. The focus is on ensuring CFET’s scalability across multiple logic nodes, with a particular emphasis on logic and SRAM scaling roadmaps.
In conclusion, the semiconductor industry is making significant strides in the development of CFET-based devices, driven by the need for improved performance and scalability. Imec’s work on backside contacting and dipole-based gate stack integration is a testament to the ongoing efforts to make CFET-based devices manufacturable and scalable. As the industry continues to innovate, CFET technology is poised to play a crucial role in the future of semiconductor manufacturing.
